`timescale 1ns / 1ps

module tb_blkRom();

parameter A_WIDTH = 4;
parameter D_WIDTH = 8;
localparam MEM_SIZE = (1 << A_WIDTH) * D_WIDTH;

reg         clk;
reg         rst;
reg         en;
reg  [A_WIDTH-1:0]  addr;

wire [D_WIDTH-1:0]  dout;

blk_mem_test blk_rom
(
    .clka   (clk),      // input wire clka
    .ena    (en),       // input wire ena
    .addra  (addr),     // input wire [3 : 0] addra
    .douta  (dout)      // output wire [7 : 0] douta
);

always #5 clk = ~clk;

integer i, j;
integer dice;
initial
begin
    clk = 0;
    rst = 1;
    #20;
    rst = 0;
    #10;
    for (i = 0; i < 16; i = i + 1) begin
        en = 0;
        dice = {$random()} % 3;
        for (j = 0; j < dice; j = j + 1) begin
            #10;
        end
        addr = i;
        en = 1;
        # 10;
    end
    en = 0;
    addr = 0;
    # 50;
    $display("Done.");
    $stop;
end

endmodule
